1. Field of the Invention
The present invention relates to a semiconductor device.
2. Description of the Background Art
A degree of integration in a semiconductor integrated circuit, particularly in an integrated circuit using a MOS transistor, has been increasing year by year. Along with the increase in the degree of integration, miniaturization of the MOS transistor used therein has progressed to a nano region. The progress in miniaturization of the MOS transistor, which constitutes an inverter circuit as a basic circuitry for digital circuits, gives rise to a problem, such as difficulty in suppressing a leak current, which causes deterioration in reliability due to hot carrier effects and poses an impediment to sufficiently reducing a circuit occupancy area while meeting a requirement of ensuring a necessary current magnitude. With a view to solving this problem, there have been proposed a surrounding gate transistor (SGT) having a structure in which a source, a gate and a drain are arranged in a direction perpendicular to a substrate, wherein the gate is formed to surround an island-shaped semiconductor layer, and a CMOS inverter circuit using the SGT (see, for example, the following Patent Documents 1 to 3).
FIGS. 1(a) and 1(b) show a conventional SGT-based two-stage CMOS inverter configured to input an output of a first inverter into a second inverter (see the following Non-Patent Document 1). A sectional view of the two-stage CMOS inverter is shown in FIGS. 2(b) and 2(c). The first inverter is made up of two pMOS SGTs 01, 02 and one nMOS SGT 03. The second inverter is made up of two pMOS SGTs 04, 05 and two nMOS SGTs 06, 07. The conventional SGT-based two-stage CMOS inverter employs a structure where a first power supply potential Vss and a second power supply potential Vcc are supplied to SGTs from respective ones of a first power supply line (Vss line) Vssl and a second power supply line (Vcc line) Vccl via corresponding ones of drain and source diffusion layers in a silicon substrate and through a plurality of contacts. Specifically, the power supply lines for the nMOS and pMOS SGTs are arranged on one side of a lower portion of a gate region which is different from an on-substrate region where the nMOS and pMOS SGTs are arranged. Generally, a resistance of a diffusion layer is extremely larger than that of a metal line for power supply. If a resistance of the first power supply line Vssl and the second power supply line Vccl increases, a source potential to be applied to each of the nMOS SGTs will increase relative to the first power supply potential Vss, and a source potential to be supplied to each of the pMOS SGTs will decrease relative to the second power supply potential Vcc. The increase in source potential of the nMOS SGT relative to the first power supply potential Vss leads to a decrease in drive current of the nMOS SGT. The decrease in source potential of the pMOS SGT relative to the second power supply potential Vcc leads to a decrease in drive current of the pMOS SGT. The decrease in drive current of each of the SGTs leads to a decrease in charge/discharge rate of a capacitance in an output terminal of the inverter. The decrease in charge/discharge rate of the capacitance in an output terminal of the inverter leads to an increase in delay time of the inverter. Therefore, a metal line is connected to the diffusion layer through a large number of contacts to apply the first power supply potential Vss to a source of each of the nMOS SGTs and apply the second power supply potential Vcc to a source of each of the pMOS SGTs.
Further, in the conventional SGT CMOS inverter, a contact is arranged on the drain diffusion layer and connected to a metal line to form an output section of the first inverter. The metal line in the output section of the first inverter is connected to a polysilicon gate as an input section of the second inverter through a contact.
Thus, in the conventional grounded substrate-type SGT-based two-stage CMOS inverter, a percentage of a contact area in a circuit occupancy area is large. Moreover, if a resistance of the first power supply line Vssl and the second power supply line Vccl increases, a delay time of the inverter will increases.
Further, in the inverter, the pMOS SGT is required to have a gate width two times greater than that of the nMOS SGT, because a hole mobility is one-half of an electron mobility.
[Patent Document 1] JP 02-071556A
[Patent Document 2] JP 02-188966A
[Patent Document 3] JP 03-145761A
[Non-Patent Document 1] S. Watanabe, K. Tsuchida, D. Takashima, Y. Oowaki, A. Nitayama, K. Hieda, H. Takato, K. Sunouchi, F. Horiguchi, K. Ohuchi, F. Masuoka, H. Hara, “A Novel Circuit Technology with Surrounding Gate Transistors (SGT'{dot over (s)}) for Ultra High Density DRAM's,” IEEE JSSC, Vol. 30, No. 9, 1995